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MS/RFMixed Signal / Radio Frequency

MS/RF 공정의 완벽한 조화

DB하이텍의 0.11um ~ 90nm MS(Mixed Signal) 공정은 World best Low noise 특성을 보유하고 있으며, Audio Codec, Touch sensor controller, Sensor ROIC 등에 최적화된 공정입니다. 또한 제품의 우수한 성능을 위해 Low Noise 소자, Thin Film Resistor, High Gain BJT 소자를 제공 중이며, 10년 이상의 풍부한 양산 경험을 바탕으로 매우 우수하고 안정적인 Yield (공정 control)를 유지하고 있습니다.

RF(Radio Frequency) 공정은 고객의 니즈에 따라 Bulk (10ohm), HRS (high resistivity substrate, >1kohm), SOI (Silicon on insulator) 등 RF 제품 디자인을 위한 다양한 옵션을 제공하고 있으며 RF front-end 용 IC (TV Tuner, Bluetooth, Switch, LNA 등)에 맞춰 가격 경쟁력과 특성을 고려한 최적의 선택을 할 수 있습니다.

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혁신적인 MS/RF 설계 지원

90nm Digital + Analog: 90nm channel length with 0.11um shrunk BEOL Support Various Vop (1.2V, 3.3V, 5V) PNO gate oxide is used for lower 1/f noise characteristics than TS11 process
(TS09 Process) eNVM : ~128Kbit Anti fuse (eMemory) Digital IP/Lib : Multi Vth Std. Cell Lib, IO Lib, Memory Compiler SPICE model including Mismatch & Noise, Cadence PDK

0.11um Digital + Analog: 0.13um channel length with 0.11um shrunk BEOL Support Various Vop (1.2V, 1.5V, 2.5V, 3.3V, 5V) ULP (Ultra Low LKG + Low Noise + Low Op.)
(TS11 Process) Optical Shrink Process (90%) of 0.13um Foundry General Process eNVM : ~32bit Poly fuse, ~512Kbit EPROM (eMemory), ~128Kbit Anti fuse (Kilopass) Digital IP/Lib : Multi Vth Std. Cell Lib, IO Lib, Memory Compiler SPICE model including Mismatch & Noise, Cadence PDK

(ULP11 Process) Focus on Low Power + Ultra Low Leakage + Low Power Operation, Able to Minimize both Active Power Consumption and Leakage in off-status in one technology PNO gate oxide is used for lower 1/f noise 1.5V Low Power & 1.2V Ultra Low LKG.

0.11μm RF Bulk CMOS: RF process compatible with optical Shrink Process (90%) of 0.13um Foundry General Process Substrate resistivity: 10ohm-cm Up to 1Poly 5~8Metal process (with UTM) Fully Characterized PDK and Industry Standard CAD Tools Inductor : Standard, Symmetric, Symmetric with Center tap.

0.11μm RF HRS CMOS: RF process (1.2V / 2.5V) compatible with optical Shrink Process (90%) of 0.13um Foundry General Process Substrate resistivity: 1kohm-cm Up to 1Poly 5Metal process (with UTM), 1Poly 2~3Metal + 1~2 UTM (Four configuration) Fully Characterized PDK and Industry Standard CAD Tools Inductor

0.13μm RF SOI CMOS: Single (2.5V) for switch or dual gate oxide process (1.2V / 2.5V) for LNA 5V CMOS + 5V LDMOS for one chip solution (Controller/PA/LNA) – ’26, Apr. Substrate: Trap-rich SOI Up to 1Poly 5Metal process (with UTM), 1Poly 2~3Metal + 1~2 UTM (Four configuration) Fully Characterized PDK and Industry Standard CAD Tools Inductor